Re: Design Verification Engineer(need H1B/Gc/USC)

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rate?

On Fri, 7 Mar 2025 at 22:12, Stacy CAP <stacy@capital-it.net> wrote:

We are looking for 

ROLE: Design Verification Engineer

 FIRST PREFERENCE CA LOCALS


Location: San Francisco, CA (onsite)

Contract:10+ Months

Job Description: https://capgemini.talentnet.community/jobs/ed4eca0b-9c59-4c72-95f0-9230572ff4f4

NEED GC/USC/H1B with PP number 


Must Have: 

  • Core Expertise: SystemVerilog UVM, SoC/Subsystem Verification, Functional Testing.
  • EDA Tools: Synopsys, Cadence, Mentor Graphics.
  • Scripting & Automation: Python, TCL, Perl, Shell.
  • High-Speed Interfaces: AXI, AHB, APB, PCIe, DDR, Ethernet.
  • Debugging & Analysis: Waveform analysis, Coverage Metrics, Root Cause Analysis.

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Thanks & Regards

Vasudev
Sr. Manager - US IT Recruitment & Bench Sales
O: 408-659-7777
Skybeyo Technologies Inc.
2603 Camino Ramon, Suite 200 San Ramon, CA 94583

* Playwright, Salesforce Certified SDET Candidates available on Bench*

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