ASIC Design Verification Engineer / San Francisco, CA

Hi Partners,

Below i have a position available on ASIC Design Verification Engineer. Please let me know if you have any candidates available.

JOB DESCRIPTION:

Title: ASIC Design Verification Engineer

Location: San Francisco, CA

Duration: 12 months

JD:

Work with researchers and architects defining verification methodologies for each of the different core IP.

Define and track detailed test plans for the different modules and top levels.

Implement scalable test benches including checkers, reference models, coverage groups in System Verilog.

Keep track of coverage metrics and bugs encountered and fixed.

Implement self-testing directed and random tests.

Support post silicon bringup and debug activities.

Ability to communicate clearly.

Primary Skills: 2+ years of System Verilog OVM/UVM DV experience.

Knowledge of Python, Perl, shell scripting. Knowledge with assertions (SVA) or others.

Knowledge of digital ASICs design flows.

Bachelor’s degree in Electrical

Engineering or Computer Science or equivalent experience.

Nice to haves:

C, C++ coding, debugging experience.

Experience as a digital design engineer.

Experience with low power design. FPGA implementation and debug experience.

Self-motivated and team player.

Masters in Electrical Engineering or Computer Science.

Thanks,

John William

Technical Recruiter

ASK Staffing Inc | Global Delivery Center

Direct: +1678-250-9920

Fax: 678-990-0403

ASK Staffing, Inc, 6495 Shiloh Rd, Suite 300, Alpharetta, GA 30005

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