Role: Xeon Validation Engineer With PCIe Experience
Hillsboro, OR(onsite)
• Should be able to interpret specifications to assist with debug and test development.
• Should have hands-on validation experience of sever functions like Reset/Boot, Storage, security, RAS, power management sub-systems, memory sub-systems, networking on Xeon platforms.
• Should have worked on PCIe and it's subsystems, preferably Gen5. PCIe flow knowledge is a plus.
• Should be familiar with Xeon CPU micro-architecture, instruction set pipeline and OOB based validation flows.
• Good understanding on debug including ITP JTAG tools, ITH, VISA, View Pin, FW.
• Good understanding of the memory flows, memory controller, CMI, DDR4/DDR5, different types of DIMM types (RDIMM etc.)
• Should have a good understanding of system power/reset/boot flows, and firmware (BIOS, BMC and CPLD, etc.) interactions during the process.
• Experience in Post-Si Test plan creation and content development along with validation.
• Hands on experience with software verification and validation using test frameworks / automation tools / scripting languages such as Python or Perl.
Warm Regards,
Bhaskar kumar | Senior Recruiter 
3S Business Corporation
kumar.koppisetti@3sbc.com
16700 HOUSE HAHL RD BLDG 6B, Cypress, TX-77433


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