Title : Protium and Palladium Engineer
Location : Menlo Park or anywhere in US
Jd :
Note : Palladium/ Protium experience is must, alternative of Palladium/Protium is “Palladium, ZeBu or HAPS/Protium"
- Port ASIC/IP RTL to Emulation platforms (Preferred: Palladium/Protium)
- Build model from released RTL based on provided methodology and BKMs.
- Generate Design image based on design configuration and test and release the image and Triage the image.
- Run Go-NoGo tests provided for qualifying release of the model
- Release the model to various team including DFx, Volume Manufacturing, Functional Validation team
- Assist debug of failure test by triaging failure and providing instrumented model
- Coordinate with Tools team to validate tool and Model release
- FPGA and Emulator flows and methodologies
- Emulator platforms (Cadence Palladium), platform bringup, digital design, verification, debugging, and waveform viewers
- Hardware emulators, such as Palladium, ZeBu or HAPS/Protium
- Emulation methodologies, including in-circuit emulation, hybrid systems, or simulation acceleration
- Programming skills in C and C++
- Scripting in Python, Tcl, or Perl
- Bring-up and debug the platform issues
- Hardware Emulation Platforms and tools
- Strong knowledge of Complete Design Cycle to understand the Different IP designs to integrate In the build
- Simulation acceleration knowledge (DPI and Transactors)
- Gate-level understanding of RTL and Synthesis
- Logic simulation: VCS/NCSIM
- Programming/scripting skills (C, C++, Python)
- Excellent communication skills, and ability to work in a fast-paced exciting environment
Thank you.
Vaibhav Kumar | VBeyond Corporation
Hangout:-vaibhavvbeyond@gmail.com
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Thanks