Hi,
Greetings of the day!
Please find the below Job description, if you are interested share your updated resume in word format
rohithm@askstaffing.com or reach me # 678-310-2898
ASIC Design Verification Engineer (9740074)
SAN FRANCISCO CA 94105
12 Months
Description
Testbench development - System Verilog UVM and C tests
Integration/development of C tests/APIs and SW build flow
Integration/development of UVM mailboxes and HW/SW communication components
Integration of lower level UVM testbenches
Test plan development
Power Aware testbench development and simulations
Seamless porting between simulation/emulation/prototyping platforms
Regression setup and debug for RTL/Gate Level Netlist/UPF PA sim/Emulation/Proto
Coverage collection and closure
Working with cross functional teams (DV/Arch/Design/FW) to identify coverage scope
MINIMUM QUALIFICATIONS
10+ years of experience in RTL Design and Verification area of which 4+ years of
experience in SoC Design Verification and HW/SW verification
2+ years of GPU or Video IP Verification
Knowledge of System Verilog UVM and vertical testbench integration
Knowledge of low level HW/SW interaction and debug
Knowledge of multi CPU and debug architectures
Experience with development of fully automated flows
PREFERRED QUALIFICATIONS
Experience with low level SW debug - disasm, Tarmac, trace
Experience with GPU architecture
Experience with coresight architecture
Experience with embedded SW low level concepts and debug - Tarmac, ROM, RAM,
linkers, elf, disasm, code sections, cache, security
Experience with coverage merging across simulation and emulation
Experience with Power Aware, low-power validation and Gate Level Netlist in Emulation
Experience with development of fully automated flows
Experience with Gate Level Simulations
Python scripting
Thanks,
Rohith M
ASK Staffing, Inc. | Global Delivery Center
Direct: 678-310-2898
Email: rohithm@askstaffing.com
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