Title: Design verification
Duration: 6 month + contract
Location: Remote is okay, preference is Boise, ID or Austin TX
Mode of interview: Video
Design verification candidates. UVM and system Verilog is a must.
We already emphasized that we're looking for strong SoC DV candidates. System-level experience is highly preferred. Familiarity with PCIe, HBM, Ethernet, or D2D is a plus. Here's a general checklist for candidates. Please have them describe their experience in these areas as part of the summary when you send candidates to me for submission.
Strong SystemVerilog and UVM skills
Scripting experience (Python/Perl/Shell) is a plus
C-based verification experience is a plus
Experience with infrastructure tasks (testbench development, VIP integration, etc.)
Solid debugging and problem-solving skills
Duration: 6 month + contract
Location: Remote is okay, preference is Boise, ID or Austin TX
Mode of interview: Video
Design verification candidates. UVM and system Verilog is a must.
We already emphasized that we're looking for strong SoC DV candidates. System-level experience is highly preferred. Familiarity with PCIe, HBM, Ethernet, or D2D is a plus. Here's a general checklist for candidates. Please have them describe their experience in these areas as part of the summary when you send candidates to me for submission.
Strong SystemVerilog and UVM skills
Scripting experience (Python/Perl/Shell) is a plus
C-based verification experience is a plus
Experience with infrastructure tasks (testbench development, VIP integration, etc.)
Solid debugging and problem-solving skills
ABHINAY KUMAR B
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