ASIC Design Verification Engineer |San Francisco, CA |12 Months
Hi,
Greetings of the day!
Please find the below Job description, if you are interested send your updated resume in word format rohithm@askstaffing.com or reach me# 678-310-2898
ASIC Design Verification Engineer
San Francisco, CA
12 Months
Description:
Work with researchers and architects defining verification methodologies for each of the different core IP.
Define and track detailed test plans for the different modules and top levels. Implement scalable test benches including checkers, reference models, coverage groups in System Verilog.
Keep track of coverage metrics and bugs encountered and fixed.
Implement self-testing directed and random tests.
Support post silicon bringup and debug activities.
Ability to communicate clearly.
Primary Skills:
2+ years of System Verilog OVM/UVM DV experience.
Knowledge of Python, Perl, shell scripting. Knowledge with assertions (SVA) or others.
Knowledge of digital ASICs design flows.
Bachelor’s degree in Electrical
Engineering or Computer Science or equivalent experience.
Nice to haves:
C, C++ coding, debugging experience.
Experience as a digital design engineer.
Experience with low power design.
FPGA implementation and debug experience.
Self-motivated and team player. Masters in Electrical Engineering or Computer Science.
Thanks,
Rohith M
ASK Staffing, Inc. | Global Delivery Center
Direct: 678-310-2898
Email: rohithm@askstaffing.com
G-Hangouts:roheeth.ta@gmail.com
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